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iNIS 2016 Will Be December 19-21, 2016 in Gwalior, India.

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The call for papers for the 2016 iNIS conference is now available...

iNIS Overview

Important Deadlines

Submission Deadline: July 18, 2016 (Extended to August 22, 2016)
Acceptance Notification: September 12, 2016 (Extended to September 30, 2016)
Camera Ready Copy Submission Deadline: October 14, 2016

The Call for Papers

iNIS is seeking submissions in 6 areas surrounding Nanoelectrics, VLSI, IoT, Hardware/Cyber Security and HW/SW solutions for Big Data. Submissions Due by July 18th August, 22nd, 2016.

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The Call for Student Research Forum

The Student Research Forum (SRF) is hosted for the benefit of research scholars and graduate students alike. All accepted submissions will be published at the conference with the top 5 published in the IEEE-iNIS proceedings. Submissions Due by July 18th August, 22nd, 2016.

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Call for Special Sessions

iNIS is seeking submissions for special sessions and panels from both academia and industry. Proposal should focus on emerging topics and new developments. Submissions Due by July 1st August, 22nd, 2016

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The Steering Committee

The steering committee is made up of 11 members. There affiliations, positions and emails can be found below.

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Technical Scope of IEEE iNIS

The primary objective of IEEE iNIS is to provide a platform for both hardware and software researchers to interact under one umbrella for further development of efficient and secure information processing circuits and systems.

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The Organizing Committee

The organizing committee currently consists of 23 members. Their positions, affiliations and emails are found below.

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Student Travel Grants and Awards

We are pleased to announce Student Travel Grants and Best Paper award at iNIS 2016: TCVLSI Best Paper Award (1) - $150 TCVLSI Student Travel (4 grants) - $250 each

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About iNIS

IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS)

(http://www.ieee-inis.org)

 

1.     Key Theme

The primary objective of IEEE iNIS is to provide a platform for both hardware and software researchers to interact under one umbrella for further development of efficient and secure information processing circuits and systems. Efficient secured data sensing, storage, and processing play pivotal roles in the current information age. State-of-the-art nanoelectronic technology based very-large-scale-integration (VLSI) systems cater to the emerging needs of efficient sensing, storage, and computing. At the same time, efficient algorithms and software used for faster analysis and retrieval of desired information are becoming increasingly important. Big data, which are large, complex data sets, are now a part of the Internet world. Storing and processing needs of the enormous amount of structured and unstructured data are getting increasingly challenging. At the same time, Internet of Things (IoT) and cyber-physical systems (CPS) have been evolving with the simultaneous development of hardware and software. The performance and efficiency of the present as well as the future generation of computing and information processing systems are largely dependent upon advances in both hardware and software.

2.     Different Tracks

1)    Nanoelectronic VLSI and Sensor Systems (NVS)

Different revolutionary and evolutionary technologies in nanoscale have evolved to cater to the need of future generation computing and information processing. Some of the thrust areas in this domain include: (a) Nanotechnologies, nanowire, nanotubes and nano-sensors, (b) Molecular electronics, bio-sensors, bio-molecular and biologically-inspired computing, (c) Nanoelectronics for energy harvesting, (d) Spintronics, domain-wall, and phase-change memories, (e) Memristor and memristive systems, (f) Advanced 3D IC technologies, design techniques, and 3D packaging, (g) On-chip interconnection network design, modeling, and simulation, (h) GPU, HPC, and large-scale cloud-based computing, (i) Quantum computing, communication, and information processing, (j) Application specific circuit, system, and sensor design using nanoelectronics, (k) Chip to System design for critical applications, (l) Electronic design automation (EDA) or computer-aided design (CAD) methods covering these areas.

 

2)    Energy-Efficient, Reliable VLSI Systems (ERS)

Consumption of energy or power dissipation has become a major issue in today’s nanoelectronic and information processing systems. Researchers are trying to address and overcome this critical bottleneck in different ways. Some of the major thrust areas are as follows: (a) Energy efficient hardware-software design and co-synthesis, (b) Energy efficient applications using field-programmable gate arrays (FPGAs), (c) Sustainability of energy efficient applications, (d) Dynamic power management, (e) Modeling, simulation, and validation, (f) Energy generation, recovery, and management systems, (g) Reliability analysis, modeling, and reliable system design, h) Low-power wearable and implantable systems, (i) Multi-core systems, Network-on-Chip, and MPSoCs, (j) Reversible Circuits and Systems, (k) Reconfigurable Systems, (l) Microfluidics and Biochips, (m) Electronic design automation (EDA) or computer-aided design (CAD) methods covering these areas.

 

3)    Hardware/Software for Internet of Things and Consumer Electronics (IoT)

IoT envisions the development of tools, techniques, and standards to make ‘things’ more intelligent and programmable to develop more capable ‘things’ to address the necessity of human beings. It covers all types of sensors, communication protocols, computational tools, techniques, devices, processors, embedded systems, data warehousing, big data, cloud computing, server farms, grid computing etc. Topics of interests include the followings: (a) IoT architecture, (b) IoT enabling technologies, services, and applications, (c) IoT system integration, management, and standards, (d) IoT big data analytics, (e) IoT security and privacy concerns, (f) IoT at nanoscale, (g) Emerging hardware/software solutions for IoT, (h) Hardware and software solutions for smart cities, (i) IoT applications in areas of healthcare, agriculture, transport, waste management, (j) Hardware and software based systems for aerotropolis, (k) emerging nanoelectronics for smart consumer electronics covering these areas.

 

4)    Hardware/Software Solutions for Big Data (SBD)

Large, complex data sets that are difficult to process using traditional data processing tools and often do not fit within the available on-board memory are traditionally called big data. Big Data presents multiple challenges including privacy, analysis, search, storage, transfer, and visualization. Novel hardware and software mechanisms are needed to address these challenges, and make Big Data useful for end users. The issues in discussion include among others, performance evaluation, optimization, accessibility, and usability of new technologies, modeling and simulation of hardware and software solutions for big data, and many more. Topics of interest include, but are not limited to the following: (a) Big Data – regression, analysis, machine learning, and exploitation, (b) Graphs and networks for big data, (c) Distributed, and scalable systems for big data, (d) Application specific systems using big data, (e) Privacy, integrity, and security in big data, (f) Storage solutions for big data, (g) Search and mining techniques in big data, (h) Hardware designs for big data covering these areas.

 

5)    Hardware for Secure Information Processing (SIP)

Due to ever increasing demand of network and information contents, hardware capacity for storage, analytics, and processing are catching the eyes of researchers to provide efficient solution to the above. Some of the thrust areas are as follows: (a) Circuits and systems for digital rights management (DRM), watermarking, and encryption, (b) Data protection strategies and controls, (c) Mobile security and bring your own device (BYOD), (d) Medical device security, (e) Cyber security, (f) Emerging embedded solutions for security covering these areas.

 

6)    Cyber Physical Systems and Social Networks (CSN)

CPS provides the efficient integration of the physical world with the information and communication technologies, to cater the needs of next generation embedded computing and information processing. Social networks are playing a dominant role in business intelligence and analytics nowadays. Special types of hardware and software are being developed to handle the enormous amount of unstructured data available via such networks. Some of the thrust areas are as follows: (a) Modeling of distributed real-time software for CPS, (b) Mobile cyber-physical systems, (c) Design challenges of CPS, (d) Data portability and management, (e) Graphs, algorithms, and Disambiguation in semantic search, (f) Special purpose architectural solution covering these areas.

The Committees

Technical Program

iNIS 2016 Program Outline
19 December 2016 (Monday) 8:00-9:00  Registration & Refreshment
9:00-9:30 Inaugural Event
9:30-10:15 Keynote # 1 : "Applications and Challenges of Bioelectrical Systems", Serge Bernard, LIRMM AND UNIVERSITY OF MONTPELLIER, FRANCE
10:15-10:30 Coffee
10:30-11:30 Session 01: Graphene Nanoribbon Devices Session 02: Special Session: Smart and Connected Health
11:30-12:30 Session 03: Sensor Systems Session 04: Hardware/Software for Internet of Things and Smart, Connected World
12:30-14:00 Lunch
14:00-15:00 Session 05: Hardware for Secure Information Processing Session 06: Special Session: Optimizing Power Converter Technology for Consumer Electronics Devices: An Indian Prospective
15:00-16:00 Session 07: Student Research Forum: Hardware & Security
16:00-16:30 Coffee
16:30-17:30 Session 08: Low Power Device Technologies
17:30-18:30 Session 09: Reliable VLSI Systems
18:30-19:00 Break TCVLSI Meeting
19:00-21:00 Dinner
       
20 December 2016 (Tuesday) 8:00-9:00 Registration
9:00-9:45 Keynote # 2 : "Theoretical and Practical Relations between Low Energy Computation and Reversible Computing Software", Kalyan Perumalla, OAK RIDGE NATIONAL LABORATORY (ORNL), USA
9:45-10:00 Coffee
10:00-11:00 Session 10: Emerging Device Technologies Session 11: Special Session: Post CMOS Computing
11:00-12:00 Session 12: Amplifier Systems Session 13: Cyber Physical Systems and Social Networks
12:00-14:00 Lunch
14:00- 16:00 Session 14: Physical Unclonable Functions for Security
16:00-16:30 Coffee
16:30-17:30 Session 15: Special Session: Turning software into hardware Ð Hastlayer Session 16: Special Session: Modeling and Usage of Nanoscale Process Variations in Emerging Technology
17:30-18:30 Session 17: Student Research Forum: Information Communication & IoT
18:30-19:00 Break iNIS Steering Committee Meeting
19:00-21:00 Cultural Event & Banquet Dinner
       
21 December 2016 (Wednesday) 8:00-9:00 Registration
9:00-9:45 Keynote # 3 : "Beyond Charge Based Computing", Kaushik Roy, PURDUE UNIVERSITY, USA.
9:45-10:00 Coffee
10:00-11:00 Session 18: Quantum and Reversible Technologies Session 19: Special Session: Cyber-Physical Power Systems: Security Threats and Counter Measures
11:00-12:00 Session 20: Biomedical VLSI Systems Session 21: Energy-Efficient VLSI Systems
12:00-14:00 Lunch
14:00-15:00 Session 22: FinFET Devices
15:00-16:00 Session 23: Special Session: An Efficient Design Methodology for CNFET based Ternary Logic Circuits Session 24: Special Session:  QSCsim Ð Charge based Switched capacitor Simulator
16:00-16:30 Coffee
16:30-17:30 Session 25: IEEE WIE
17:30-18:00 Closing Remarks and Award Ceremony
Intentionally left Blank
iNIS 2016 Program Details
19 December 2016 (Monday) 8:00-9:00  Registration & Refreshment
9:00-9:30 Inaugural Event
9:30-10:15 Keynote # 1 : "Applications and Challenges of Bioelectrical Systems", Serge Bernard, LIRMM AND UNIVERSITY OF MONTPELLIER, FRANCE
Chair: Saraju Mohanty, UNT
10:15-10:30 Coffee
10:30-11:30 Session 01: Graphene Nanoribbon Devices
Chair: Anurag Srivastava, IIITM, Gwalior
Session 02: Special Session: Smart and Connected Health
Chair: Aditya Trivedi, IIITM, Gwalior
"Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design", Md Fahad, Zhou Zhao, Ashok Srivastava and Lu Peng "Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems", Prabha Sundaravadivel, Saraju Mohanty, Elias Kougianos, Prasanth Yanambaka and Himanshu Thapliyal
"Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency Applications", Yaser M. Banadaki and Ashok Srivastava
"IoT Based Fall Detection for Smart Home Environments", Shalom Greene, Himanshu Thapliyal and David Carpenter
ÒPerformance Analysis of Top-contact MLGNR based InterconnectsÓ, Ramesh Kumar, Rohit Dhiman and Rajeevan Chandel
11:30-12:30 Session 03: Sensor Systems
Chair: Anupam Shukla, IIITM, Gwalior
Session 04: Hardware/Software for Internet of Things and Smart, Connected World
Chair: Mahua Bhattacharya, IIITM, Gwalior
"Ni-CNT as isopropanol sensor: ab-initio analysis", Sushmita Dandeliya, Md Shahzad Khan and Anurag Srivastava "Design and implementation of tunable bandpass filter for Biomedical Applications", Saurabh B.K., Nithin Kumar Y.B., Shivnarayan Patidar and Vasantha M.H.
"CMOS-Memristor Hybrid Integrated Pixel Sensors", Kamilya Smagulova, Aigerim Tankimanova and Alex Pappachen James ÒA 4X1 High-Definition Transcranial Direct Current Stimulation Device for Targeting Cerebral Micro Vessels and Functionality using NIRSÓ, Gaurav Sharma, Yashika Arora and Shubhajit Roy Chowdhury
ÒA Reply Cache Mechanism to reduce Query Latency of WSN in IoT Sensory EnvironmentÓ, Yeduri Sreenivasa Reddy and K. K. Pattanaik "An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems", Pranshu Kalra, Shaista Hussain and Nitin Chaturvedi
12:30-14:00 Lunch
14:00-15:00 Session 05: Hardware for Secure Information Processing
Chair: K.K. Mahapatra, NITR
Session 06: Special Session: Optimizing Power Converter Technology for Consumer Electronics Devices: An Indian Prospective
Chair: Santanu Mishra
"Securing IEEE 1687 Standard On-chip Instrumentation Access using PUF", Sudeendra kumar K, Naini Satheesh, Abhishek Mahapatra, Sauvagya Sahoo and K.K.Mahapatra "Power Converter Systems for Consumer Electronics Devices", Santanu Mishra
"Hardware Security Threats to DSP Applications in an IoT network", Azhar Syed and Mary Lourde R
"Area and Throughput Analysis of Different AES Architectures for FPGA Implementations", Disha Yadav and Arvind Rajawat
15:00-16:00 Session 07: Student Research Forum: Hardware & Security
Chair: Anirban Sengupta, IITI
"Graphene Nanoribbon Field Effect Transistor based Ultra-Low Energy SRAM Design", Shital Joshi, Saraju Mohanty, Elias Kougianos and Prasanth Yanambaka
"Protecting Ownership of Reusable IP Core Generated during High Level Synthesis", Deepak Kachave, Anirban Sengupta
16:00-16:30 Coffee
16:30-17:30 Session 08: Low Power Device Technologies
Chair: Susanta Chakraborty, IIEST, Shibpur
"Performance Analysis of Wavy FinFET And Optimization for Leakage Reduction", Anju C, Nisha Kuruvilla, Ayoob Khan T E and Shahul Hameed T A
"Novel Ultra Low Leakage FinFET Based SRAM Cell", Vivek Kumar, Vikas Mahor and Manisha Pattanaik
ÒVariation Aware Performance Analysis of TFETs for Low-Voltage ComputingÓ, Vikash Sehwag, Saurav Maji and Mrigank Sharad
17:30-18:30 Session 09: Reliable VLSI Systems
Chair: Manisha Pattanaik, IIITM, Gwalior
"A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects", Ojashri Sharma, Aakash Saini, Sandeep Saini and Abhishek Sharma
"An Efficient Approach Targeting Broken Topological Clock Path for Master Ð Generated Clock Pair", Pawan Sehgal, Akhilesh C. Mishra, Rangarajan Ramanujam and Sujay Deb
"Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip", Ayas Kanta Swain,Anil Kumar Rajput and Kamalakanta Mahapatra
18:30-19:00 Break TCVLSI Meeting
19:00-21:00 Dinner
       
20 December 2016 (Tuesday) 8:00-9:00 Registration
9:00-9:45 Keynote # 2 : "Theoretical and Practical Relations between Low Energy Computation and Reversible Computing Software", Kalyan Perumalla, OAK RIDGE NATIONAL LABORATORY (ORNL), USA
Chair: G. K. Sharma, IIITM, Gwalior
9:45-10:00 Coffee
10:00-11:00 Session 10: Emerging Device Technologies
Chair: Nitin Chaturvedi, BITS, Pilani
Session 11: Special Session: Post CMOS Computing
Chair: Prasun Ghosal, IIEST, Shibpur
"Aromaticity Influence on Electron Transport of Molecular Single Electron Transistor: DFT Investigation", Boddepalli SanthiBhushan, Anurag Srivastava, Jyoti Bhadouria, Rinkoo Bhatia and Pankaj Mishra "Post CMOS Computing Beyond Si: DNA Computer as Future Alternative", Prasun Ghosal and Mayukh Sarkar
"Proposal of Heterogate Technique for Performance Enhancement of DM-TFET", Chaitanya Maradana and Jawar Singh "A Provably Good Method to Generate Good DNA Sequences", Swapan Shakhari, Prasun Ghosal and Mayukh Sarkar
"Investigation of DC Characteristic on DG-Tunnel FET With high-K Dielectric Using Distinct Device Parameter", Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav and Santosh K. Vishvakarma
11:00-12:00 Session 12: Amplifier Systems
Chair: Shahikala Tapaswi, IIITM, Gwalior
Session 13: Cyber Physical Systems and Social Networks
Chair: K. K. Mahapatra, NITR
"A 60 dB Bulk-driven Rail-to-Rail Input/Output OTA", Abhishek Shrivastava, Ajay Pratap Gangwar, Rahul kumar and Rohit Dhiman "An Edge Contribution-Based Approach to Identify Influential Nodes from Online Social Networks", Samya Muhuri, Susanta Chakraborty and S.K. Setua
ÒA 0.5V Voltage-Combiner based Pseudo Differential OTA design in CMOS using Weakly inverted TransistorsÓ, Antaryami Panigrahi and Abhipsa Parhi "Na•ve Bayes Approach for Predicting Missing Links in Ego Networks", Anand Kumar Gupta and Neetu Sardana
"Mixed-Mode Simulation of Common Emitter Amplifier Design using Bipolar Charge Plasma Transistor", Chitrakant Sahu and Nitesh Agrawal "A Neural Network-based Appliance Scheduling Methodology for Smart Homes and Buildings with Multiple Power Sources", Raj Mani Shukla, Prasanna Kansakar and Arslan Munir
12:00-14:00 Lunch
14:00- 16:00 Session 14: Physical Unclonable Functions for Security
Chair: Susanta Chakraborty, IIEST, Shibpur
"Novel FinFET based Physical Unclonable Functions for Efficient Security Integration in the IoT", Venkata P. Yanambaka, Saraju P. Mohanty and Elias Kougianos
"A Modified RO-PUF with Improved Security Metrics on FPGA", Naini Satheesh, Abhishek Mahapatra, Sudeendra kumar K, Sauvagya Sahoo and K.K.Mahapatra
"TV-PUF : A Fast Lightweight Analog Physical Unclonable Function", Vikash Sehwag and Tanujay Saha
"A Novel Aging Tolerant RO-PUF for Low Power Application", Sudeendra Kumar and Kamalakanta Mahapatra
16:00-16:30 Coffee
16:30-17:30 Session 15: Special Session: Turning software into hardware Ð Hastlayer
Chair: Zolt‡n Leh—czky
Session 16: Special Session: Modeling and Usage of Nanoscale Process Variations in Emerging Technology
Chair: K. V. Arya, IIITM, Gwalior
"Turning software into hardware Ð Hastlayer", Zolt‡n Leh—czky, Rich‡rd T—th, Andr‡s Retzler, M‡rk Bartha, Benedek Farkas and Kriszti‡n Somogyi "Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors", Meena Panchore, Jawar Singh, Saraju P Mohanty and Elias Kougianos
"Secure Multi-Key Generation Using Ring Oscillator based Physical Unclonable Function", Saraju Mohanty, Elias Kougianos, Prasanth Yanambaka, Jawar Singh
17:30-18:30 Session 17: Student Research Forum: Information Communication & IoT
Chair: Anirban Sengupta, IITI
"Classification of Non-Functional Requirements from SRS documents using Thematic roles", Prateek Singh, Deepali Singh and Ashish Sharma
"A Computation Offloading Scheme Leveraging Parameter Tuning for Real-Time IoT Devices", Raj Mani Shukla and Arslan Munir
18:30-19:00 Break iNIS Steering Committee Meeting
19:00-21:00 Cultural Event & Banquet Dinner
       
21 December 2016 (Wednesday) 8:00-9:00 Registration
9:00-9:45 Keynote # 3 : "Beyond Charge Based Computing", Kaushik Roy, PURDUE UNIVERSITY, USA.
Chair: Ashok Srivastava, LSU
9:45-10:00 Coffee
10:00-11:00 Session 18: Quantum and Reversible Technologies
Chair: Rajendra Sahu, IIITM, Gwalior
Session 19: Special Session: Cyber-Physical Power Systems: Security Threats and Counter Measures
Chair: B. K. Panigrahi, IITD
"Optical Characteristics of Solution Processed MoO2/ZnO Quantum Dots based Thin Film Transitor", Hemant Kumar, Yogesh Kumar, Gopal Rawat, Chandan Kumar, Bhola N Pal and Satyabrata Jit "Bid Modification Attack in Smart Grid for Monetary Benefits", Kush Khanna, Bijaya Ketan Panigrahi, and Anupam Joshi
"Electrical and optical characteristics of Pd/ZnO Quantum dots based Schottky Photodiode on n-Si", Yogesh Kumar, Hemant Kumar, Gopal Rawat, Chandan Kumar, Bhola.N Pal and S. Jit
ÒDesign of ESOP-RPLA Array using DRG2 and DRG4 Gates based on Reversible Logic TechnologyÓ, Anurag Govind Rao and Dr. Anil Kumar Dhar Dwivedi
11:00-12:00 Session 20: Biomedical VLSI Systems
Chair: Manisha Pattanaik, IIITM, Gwalior
Session 21: Energy-Efficient VLSI Systems
Chair: Pankaj Srivastava, IIITM, Gwalior
"Computing in Ribosomes: Implementing Sequential Circuits using mRNA-Ribosome System", Pratima Chatterjee, Mayukh Sarkar and Prasun Ghosal "Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application", Govinda Sannena and Bishnu Prasad Das
"Memristor Crossbar-based Pattern Recognition Circuit using Perceptron Lerning Rule", Muhammad Khalid and Jawar Singh "LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder", Pritam Bhattacharjee and Alak Majumder
"Mathematics using DNA: Performing GCD and LCM on a DNA Computer", Mayukh Sarkar and Prasun Ghosal "Energy detection based dynamic spectrum sensing for 2.4GHz ISM band", Saket Srivastava, Mohammad Hashmi, Supratim Das and Dibakar Barua
12:00-14:00 Lunch
14:00-15:00 Session 22: FinFET Devices
Chair: Anurag Srivastava, IIITM, Gwalior
"Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs", Rituraj Singh Rathore, Rajneesh Sharma and Ashwani K. Rana
"Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k spacer FinFET", Nandakishor Yadav, Ankur Beohar and Santosh K. Vishvakarma
"Low Stand-by Power and Process Variation Tolerant FinFET based SRAM cell", Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor and Manisha Pattanaik
"FinFET-based Low Power Address Decoder under Process Variation", Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor and Manisha Pattanaik
15:00-16:00 Session 23: Special Session: An Efficient Design Methodology for CNFET based Ternary Logic Circuits
Chair: M. B. Srinivas, BITS, Pilani
Session 24: Special Session:  QSCsim Ð Charge based Switched capacitor Simulator
Chairs: Binsu J Kailath and Dinesh Ganesan
"An Efficient Design Methodology for CNFET based Ternary Logic Circuits", Chetan Vudadha, Sai Phaneendra P and M.B. Srinivas "QSCsim Ð Charge based Switched Capacitor Simulator", Binsu J Kailath and Dinesh Ganesan
16:00-16:30 Coffee
16:30-17:30 Session 25: IEEE WIE
Chair: Manisha Pattanaik, IIITM, Gwalior
 
17:30-18:00 Closing Remarks and Award Ceremony

Keynotes

Kaushik Roy

Purdue University, USA.

Abstract

Beyond Charge Based Computing
Recent experiments on spin devices like magnetic tunnel junctions (MTJ), domain wall magnets (DWM) and lateral spin valves (LSV) have led to the possibility of using "spin" as state variable for computation. While the possibility of on-chip spin transfer torque memories is close to reality, several questions still exist regarding the energy benefits of spin for logic computation. Lateral spin valves (LSV) involve switching of nano-magnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for low power Boolean as well as Non-Boolean computation like cognitive/neuromorphic computing, associative memory, programmable logic and analog and digital signal processing. Simulation results for these applications based on a calibrated device-circuit co-simulation framework predict two orders of magnitude improvement in computation energy as compared to state of the art CMOS design.

Brief Biography

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, supervised 70 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Serge Bernard

LIRMM and University of Montpellier, France

Abstract

Applications and Challenges of Bioelectrical Systems
Implanted or portable electrical systems can be precious in both biological and medical areas. First, they can be used for diseases when drug treatments are inefficient. As illustration, the well-known Functional Electrical Stimulation (FES) techniques are one possible alternative to restore lost sensory or motor abilities due to neural system pathologies such as spinal cord injury. It consists in replacing the natural direct muscle activation by electrical stimulation which can evoke an artificial contraction. FES can be performed using surface electrodes but implanted FES is the only solution for daily use context outside a clinical environment. Electrical implants or devices are not only suitable for disease treatment; they can also serve as new tools for increasing knowledge in biology or medicine. In this keynote, we will see a wide range of applications, from the most mature ones like pacemaker device to the more research-level like visual implants. We will also discuss about associated challenges and the key trends of this field.

Brief Biography

Dr. Serge Bernard is researcher of the National Council of Scientific Research (CNRS) in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) in the south of France. He received the MS degree in Electrical Engineering from the University of Paris XI, France in 1998 and the PhD degree in Electrical Engineering from the University of Montpellier, France in 2001. His main research interests include Test, Design-For-Testability and Built-In-Self-Test for mixed-signal circuits and SiP and Design-For-Reliability for medical application ICs. Dr. Serge Bernard is an inventor of 3 US patents. He has supervised 14 PhD dissertations. He is an author of 110 peer-reviewed international journal and conference articles, and contributed to the redaction of 2 books. Dr. Bernard served as General Chair on the IEEE International Mixed-Signal Testing Workshop (IMSTW’15) and on the IEEE Design of Circuits and Integrated System (DCIS'2012). He served as Program-Chair on the IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS'14) and on the IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, (DTIS'11). He has served as guest editor in Microelectronics Journal (MEJO). He serves on the organizing and program committees of several international conferences. He serves on the steering committee of the IEEE Design of Circuits and Integrated System (DCIS). He is founder and he was the director of the joint Institute for System Testing (ISyTest) between the LIRMM and NXP semiconductors. He has been the head of the microelectronics department of LIRMM for three years. Dr. Bernard has been involved in several European research projects (MEDEA+ ASSOCIATE, IST EuNICE-Test, MEDEA+ NanoTEST, CATRENE TOETS, ENIAC JU ELESIS).

Kalyan Perumalla

Oak Ridge National Laboratory (ORNL), USA

Abstract

Theoretical and Practical Relations between Low Energy Computation and Reversible Computing Software
With the recently increasing research emphasis on circuits with very low energy consumption profiles, including switching at the Landauer limit of heat dissipation, circuit designs are poised to encounter fundamental theoretical and practical relations of low energy computation with reversibility of computation. At the same time, advancement in high performance parallel computing is facing challenges of scale that can also be addressed by rendering the very parallel execution reversible. The appearance of reversibility as a fundamental aspect across these two extreme scales of computing brings into focus the new need to infuse reversibility into computer programming software, serial or parallel. In this backdrop, the talk outlines the theoretical aspects of reversibility in circuits and general-purpose computation, recounts salient aspects such as the Landauer limit and the Bennett trick, and describes the role of reversibility in large-scale parallel computing such as with the impending exascale systems. Reversible computing-based approaches, with a focus on their immense software-level challenges, will be presented aimed at fault tolerance, parallel synchronization, and debugging for usability, at very large parallel processing scales.

Brief Biography

Kalyan Perumalla, Ph.D., is a Distinguished R&D staff member and manager at the Oak Ridge National Laboratory. He is the founding Group Leader of the Discrete Computing Systems Group in the Computational Sciences and Engineering Division. He also serves as an adjunct professor in the School of Computational Sciences and Engineering at the Georgia Institute of Technology. He has published his research and delivered invited lectures and tutorials on topics spanning high performance computing and simulation. His recent book Introduction to Reversible Computing is among the first few in its area. He co-authored another monograph, three book chapters, and over 100 articles in peer-reviewed conferences and journals. Five of his co-authored papers received the best paper awards, in 1999, 2002, 2005, 2008 and 2014. His research prototypes in parallel and distributed computing have been disseminated to research institutions worldwide. He earned his Ph.D. in computer science from the Georgia Institute of Technology in 1999. Dr. Perumalla is a winner of the US Department of Energy Early Career Award in Advanced Scientific Computing Research, 2010-2015, providing $2.5 million for basic research dedicated to reversible computing solutions at Exascale. In 2015, he was selected as a Fellow of the Institute of Advanced Study at the Durham University, UK. He has been nominated to serve on the National Academy of Sciences’ Technical Advisory Board on Information Science at the US Army Research Laboratory, 2015-2017. Dr. Perumalla serves as program committee member, editorial board member, and reviewer for multiple international conferences and journals in computing. He has performed over the past 15 years as principal investigator and co-principal investigator on research and development projects sponsored by the Department of Energy, Department of Homeland Security, DARPA, Army Research Laboratory, National Science Foundation, and industry.

The Venue

The Conference Venue

Syndicate Hall-205 and 211, Second Floor, ABV-IIITM campus, Morena Link Road - 474010, Gwalior, India. Phone: +91 751 2449826 | 2449734. It is at a 2 min walking distance from MDP Centre, institute guest house and 10-15min from other staying places suggested below.

Where to Stay?

There are many hotels in city, budget as well as luxury. Besides this institute also has a well-furnished guest house and International visitor’s hostel in campus. Following are details of hotels.

Luxury Hotel 4 star

The Central Park Hotel

Opp Vishal Megmart, Madhav Rao Scindia Marg, City Center, Patel Nagar, Gwalior, Madhya Pradesh 474001 Phone: +91 0751 401 1140

ROOMS CATEGORY

SINGLE

(IN RS.) CP Plan

DOUBLE

(IN RS.) CP Plan

EXECUTIVE

3000.00 + taxes

(Rs. 3261.00 CPAI)

3750.00 + taxes

(Rs. 4452.00 CPAI)

PREMIUM

3500.00 + taxes

(Rs. 4155.00 CPAI)

4250.00 + taxes

(Rs. 5045.00 CPAI)

DELUXE SUITE

6400.00 + taxes

(Rs. 7597.00 CPAI)

6400.00 + taxes

(Rs. 7597.00 CPAI)

GRANDE SUITE

9000.00 + taxes

(Rs. 10683.00 CPAI)

9000.00 + taxes

(Rs. 10683.00 CPAI)

Hotel Landmark, Gwalior { M.P }

47, Manik Vilas Colony Jhansi Road Gwalior { MP } Landline : 0751-4011271, 4011272, 4011273 Mobil.No. :09301106254, 09826224907 Deluxe Single         @ 2500/- CPAI, Double @ 2800/- CPAI Superior Single       @ 2800/- CPAI, Double @ 3000/- CPAI Executive Suite       @ 6000/- CPAI Extra Bed @ 850/-

Budget Hotel 3 star

The Hotel Vinayak Maharani Laxmibai Marg, Padav, Gwalior, Madhya Pradesh 474002, Phone:+91 0751 244 6901

 

Single

Double

Extra Bed

Royal Club

1900

2400

500

   Premium Club

2400

2900

500

20% discount to iNIS-2016 participants + Tax as applicable

Institute Guest House

MDP Centre, Near Directors Bungalow, IIITM Campus, Morena Link Road, Gwalior, Madhya Pradesh 474010, Phone: +91-751-2449616

 

Single

Double

Premium

750

1250

Suite

2500

3200

Institute has agreed to provide 30% discount

Luxury Hotel 5 star

Usha Kiran Palace, Gwalior

A Taj Group, Usha Kiran Palace, Gwalior, Jayendraganj, Lashkar, Gwalior, Madhya Pradesh 474009, Phone: +91 0751 244 4000.

Hotel administration has agreed to provide 10% discount to iNIS-2016 participants. iNIS 2016 organizers strongly suggest delegates/authors to book rooms in these hotels/guest house as rooms are blocked for the meeting on discounted rates.

How to Book?

All the guests can book their rooms by sending their reservation details on nstomar06@gmail.com, mentioning their name, check in and check out dates, estimated time for arrival, single/double occupancy and also they need to mention that the booking is in reference of iNIS-2016, ABV-IIITM, Gwalior to obtain the specially discounted rate.

Contact Details: Narendra Singh Tomar,

Phone: + 91 751 2449616, Mobile: +91 989311559

Deadline to Book: 30 November 2016

Getting to and Enjoying Gwalior

Travel

Reaching Gwalior

By Air

Gwalior city is one of the largest city in the state of Madhya Pradesh state. For reaching the city by AIR, Gwalior Airport (IATA Code: GWL) is there to welcome you. It is well connected with Delhi, Mumbai and other cities of Madhya Pradesh. Gwalior airport is named as “Rajmata Vijayraje Scindia Airport”

By Train

Gwalior junction is the main railway station for this city. Almost all long route trains stops here along with express trains like Bhopal Shatabdi. Taj Express. Bhopal Express. GT Express, Chennai Rajdhani Express etc. One can reach Gwalior railway station from important cities of India and tourist destinations like Agra, Ahmedabad, Bhopal ,Delhi, Mumbai, Pune, Chennai ,Bangalore, Kolkata , Hyderabad , Nagpur , Ujjain, Varanasi, Jaipur , Udaypur, Amratsar, Haridwar, Bharatpur, Dehradun etc. City has 2 more small stations Gwalior Birla Nagar & Gwalior Sithouli, mainly used by local small route trains. Here, we can see both narrow gauge and broad gauge railway lines which are actively used by the passenger trains.

By Road

Gwalior city is almost on border of Central India & North India. It is north of Madhya Pradesh state having road connectivity with important cities and tourist destinations like Agra, Delhi, Chambal Sanctuary, Jaipur, Ranthambhore, Bhopal, Khajuraho, Shivpuri etc. India's important highway projects like North-South Corridor and Golden-Quadrilateral, passes through Gwalior. National Highway-3 that connects Agra with Mumbai, passes through this city. Jhansi is connected with Gwalior through National Highway-75. Similarly, some state highways also connects Gwalior to other towns of Madhya Pradesh state like Indore, Jabalpur, Bhopal etc. Regular bus service are available for reaching Gwalior. You can get bus from Delhi, Agra, Panna, Chatarpur, Jhansi, Bhopal, Datia etc. to reach Gwalior.

Reaching ABV-IIITM Gwalior from various parts of the country

By Train/ Road /Air: Gwalior is well connected to all the major cities of India like New Delhi, Mumbai, Bangalore, Chennai, Hyderabad, Kolkata, Pune, Roorkee, Ambala, Ahmedabad and Lucknow. Gwalior is about 310 km from Delhi, 110 km from Agra and 420 km from Bhopal. From Gwalior Railway Station/ Bus Stand to ABV – IIITM Campus is hardly 7-8 Km. You can also reach ABV-IIITM by auto rickshaw charges Rs. 70-100 from railway station or bus stand. From Airport, the IIITM campus is about 10 km and taxi charges are Rs. 300-400.

Places to Visit in Gwalior

This sun temple is dedicated to the Sun god, located near residency at Morar, Gwalior. It is a facsimile of the famous Sun temple of Konark, Orissa and now this sun temple is one among the significant pilgrimage centres in Gwalior. The temple is located in a serene ambience and a well-maintained garden within the temple premises is very attractive. This holy temple draws the locals and tourists alike who gather here to render their prayers. It makes one astounded that a shrine of comparatively modern origin holds such a highest regard, and became one among the most sought after pilgrimage centers in the city.

Other Places to Visit

One of India's most famous cities, Agra is home to the breathtaking white-marble Taj Mahal, a truly magnificent Mughal riverside mausoleum and World Heritage Site. Agra lies in the state of Uttar Pradesh, in North India, and this region is home to no less than three designated World Heritage Sites. Agra's Taj Mahal is one of the most famous buildings in the world, the mausoleum of Shah Jahan's favourite wife, Mumtaz Mahal. It is one of the New Seven Wonders of the world, and one of three World Heritage Sites in Agra. Completed in 1653, the Tāj Mahal was built by the Mughal king Shāh Jahān as the final resting place for his beloved wife, Mumtāz Mahal. Finished in marble, it is perhaps India's most fascinating and beautiful monument.

Sponsorship

 Sponsorship of an international conference represents an organization's innovations, developments, and capabilities of the world of eminent scientists and engineers who are from academia and industry. The opportunities of iNIS sponsorship are available on a first-come, first-serve basis. So organizations are advised to reserve the opportunity that spotlights the organization's name. The following table gives a summary of benefits that possibly an organization can get at iNIS.

 

Sponsorship

Categories

Sponsorship

Fees (US $)

Sponsorship Privileges from iNIS

Silicon

8,000

1)    The sponsor's name would be displayed synonymously with iNIS.

2)    Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.

3)    Logo on the conference badge, along with the conference logo

4)    Logo on the conference bag, along with the conference logo

5)    Logo on sponsors’ choice item FCFS, from: Conference mug, pen, water bottle, visiting Card Holder

6)    Registration fee will be waived off for upto 12 delegates from the sponsor.

7)    Coverage in print media as per conference's publicity plan that gets to be in place.

Platinum

6,000

1)    The sponsor would be considered as an associate sponsor and its name would be displayed on every poster of iNIS.

2)    Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos

3)    Coverage in print media as per conference's publicity plan that gets to be in place.

4)    Registration fee will be waived off for upto 8 delegates from the sponsor.

Gold

4,000

1)    The sponsor would be a co-sponsor and its name would be displayed on very poster of the iNIS.

2)    Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.

3)    Coverage in print media as per conference’s publicity plan that gets to be in place.

4)    Registration fee will be waived off for upto 6 delegates from the sponsor.

Silver

2,000

 

1)    Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.

2)    Coverage in print media as per conference's publicity plan that gets to be in place.

3)    Registration fee will be waived off for upto 4 delegates from the sponsor.

Bronze

1,000

1)    Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.

2)    Coverage in print media as per conference's publicity plan that gets to be in place.

3)    Registration fee will be waived off for upto 2 delegates from the sponsor.

 

NOTE:

·       In addition to the above, other negotiable sponsorship is possible on case-to-case basis. Please contact General Chairs and Finance Chairs using the contact information available in the website. The objective is to encourage maximum participation and get maximum support from community of scholars.

·       In case of common item of interest, higher sponsorship package sponsors will be given the first preference, if applicable.

·       Logos to be provided by the sponsor as per conference's specifications; All content for display material, banners, backdrops, advertisements, to be put up as part of sponsorships collaterals, will have to be supplied by the sponsors, in the formats required, within the timelines specified.

·       The payments may be in US $ or Indian National Rupee (INR). With sponsors taking care of and responsible for ensuring prevailing conversion rates - from whatever currency into Indian rupees, on the day of remittance.